December 21st to 23rd 2017
Training on System Design using VHDL
- Students pursuing B.E/ B. Tech from ECE, EI, EEE who require industrial training or projects
- Student pursuing M.E./M. Tech, M.Sc Physics/ Electronics interested in hardware design.
Each Participant will be given hands-on experience in the following:
- VLSI and RTL design
- VHDL synthesis and simulation
- Implementing models in CPLD
- Each Participant will be provided with a mini-laboratory which contains all the necessary electronic hardware, software, CPLD board and tools required during the workshop. This mini-laboratory will be the property of the participants.
- Participants will be certified after successful completion of the workshop.
Last date for registration: Dec 15th 2017
Fees: 3000 GST@18% payable Extra
(Hostel facilities available)
Prof. Bhushan Patil – 88067 77865
Prof. Amit Patwardhan – 82378 16916
Prof. Rabinder Henry – 99237 00296
Colleges requiring Verilog training can contact: firstname.lastname@example.org